Fault-tolerant adder design in quantum-dot cellular automata

Document Type: Reasearch Paper


Department of Computer Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran


Quantum-dot cellular automata (QCA) are an emerging technology and a possible alternative for faster speed, smaller size, and low power consumption than semiconductor transistor based technologies. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. This paper utilizes the QCA characteristics to design a fault-tolerant adder that is more powerful in terms of implementing robust digital functions. By considering two-dimensional arrays of QCA cells, fault properties of such block adder can be analyzed in terms of misalignment, missing and dislocation cells. In order to verify the functionality of the proposed device, some physical proofs are provided. The results confirm our claims and its usefulness in designing digital circuits.


Main Subjects

[1] Lent C. S., Tougaw P. D., (1993), Lines of interacting quantum-dot cells: A binary wire. J. Appl. Physics. 74: 6227-6233.

[2] Fijany A., Toomarian B. N., (2001), New design for quantum dots cellular automata to obtain fault tolerant logic gates. J. Nanopart. Res. 3: 27-37.

[3] Farazkish R., Khodaparast F., Navi K., Jalali A., (2010), Design and characterization of a novel inverter for nanoelectronic circuits. Int. Conf. Nanotechnology: Fundamentals and Applications 219.

[4] Farazkish R., Navi K., (2012), New efficient five-input majority gate for quantum-dot cellular automata. J. Nanopart. Res. 14: 1252-1256.

[5] Farazkish R., Sayedsalehi S., Navi K., (2012), Novel design for quantum dots cellular automata to obtain fault-tolerant majority gate. J. Nanotech. Article ID 943406.

[6] Farazkish R., (2014), A new quantum-dot cellular automata fault-tolerant five-input majority gate. J. Nanopart. Res. 16: 2259-2263.

[7] Farazkish R., (2015), A New Quantum-Dot Cellular Automata Fault-Tolerant Full-Adder. J. Comput. Electronics. 14: 506-509.

[8] Farazkish R., Khodaparast F., (2015), Design and characterization of a new fault-tolerant full-adder for quantum-dot cellular automata. Microproc. Microsyst. 39: 426-433.

[9] Farazkish R., (2016), New Efficient Fault-Tolerant Full-Adder for Quantum-Dot Cellular Automata. Int. J. Nanosci. Nanotech. In Press, Corrected Proof.

[10] Azghadi M. R., Kavehei O., Navi K., (2007), A novel design for quantum-dot cellular automata cells and full-adders. J. Appl. Sci. 7: 3460-3468.

[11] Navi K., Farazkish R., Sayedsalehi S., Azghadi M. R., (2010), A new quantum-dot cellular automata full-adder. Microelect. J. 41: 820-826.

[12] Navi K., Sayedsalehi S., Farazkish R., Azghadi M. R., (2010), Five-input majority gate a new device for quantum-dot cellular automata.  J. Comput. Theoret. Nanosci. 7: 1546-1553.

[13] Navi K., Moayeri M., Faghih Mirzaee R., Hashemipour O., Mazloom Nezhad B., (2009), Two new low-power Full-Adders based on majority-not gates. Microelect. J. 40: 126-130.

[14] Hashemi S., Farazkish R., Navi K., (2013), New quantum dot cellular automata cell arrangements. J. Comput. Theoret. Nanosci.  10: 798-809.

[15] Zhang R., Walnut K., Wang W., Jullien G. A., (2004), A method of majority logic reduction for quantum cellular automata. IEEE Transact. Nanotech. 3: 443-450.

[16] Zhi H., Zhang Q., Haruehanroengra S., Wang W., (2006), Logic optimization for majority gate based nanoelectronic circuits. Int. Symposium on Circuits and Systems ISCAS. 1307-1310.

[17] Rezaei A., Saharkhiz H., (2016), Design of low power random number generators for quantum-dot cellular automata. Int. J. Nano Dimens. 4: 308-320.

[18] Azari A., Zabihi S. A., Seyyedi S. K., (2012), Conductance in quantum wires by three quantum dots arrays. Int. J. Nano Dimens. 2: 213-216.

[19] Tougaw P. D., Lent C. S., (1994), Logical devices implemented using quantum cellular automata. J. Appl. Phys. 75: 1818-1825.

[20] Cho H., Swartzlander E. E., (2007), Adder designs and analyses for quantum-dot cellular automata. IEEE Transact. Nanotechnol. 6: 374-384.

[21] Cho H., Swartzlander E. E., (2009), Adder and multiplier design in quantum-dot cellular automata. IEEE Transact. Computers. 58: 721-727.

[22] Wang W., Walus K., Jullien G. A., (2003), Quantum-dot cellular automata adders. Proceeding of the IEEE Conf. Nanotechnology.

[23] Armstrong C. D., Humphreys W. M., (2003), The development of design tools for fault tolerant quantum dot cellular automata based logic. Second International Workshop on Quantum Dots for Quantum Computing and Classical Size Effect Circuits.

[24] Armstrong C. D., Humphreys W. M., Fijany A., (2003), The design of fault tolerant quantum dot cellular automata based logic. 11th NASA Symposium on VLSI Design.

[25] Beard M. J., (2006), Design and simulation of fault-tolerant quantum-dot cellular automata (QCA) NOT gates. M. S. Thesis in Wichita State University.

[26] Dalui M., Sen B., Sikdar B. K., (2010), Fault tolerant QCA logic design with coupled majority-minority gate. Int. J. Computer Applic. 1: 81-87.

[27] Sen B., Ganeriwal S., Sikdar B. K., (2013), Reversible logic-based fault-tolerant nanocircuits in QCA. ISRN Electronics. Article ID 850267.

[28] Tahoori M. B., Momenzadeh M., Huang J., Lombardi F., (2004), Defects and faults in quantum cellular automata at nanoscale. IEEE VLSI Test Symposium 4.

[29] Huang J., Momenzadeh M., Tahoori M. B., Lombardi F., (2004), Design and characterization of an and-or-inverter (AOI) gate for QCA implementation. GLSVLSI. 26-28.

[30] Lent C. S., Tougaw P. D., (1996), Dynamic behavior of quantum cellular automata. J. Appl. Physics. 80: 4722-4736.

[31] Halliday D., Resnick A., (2004), Fundamentals of Physics. 7th Edition New York: John Wiley & Sons, Inc, Part 1, Chapters 3-6.