Channel thickness dependency of high-k gate dielectric based double-gate CMOS inverter

Document Type: Reasearch Paper

Authors

1 Department of Electronics & Communication Engineering, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.

2 Department of ECE, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.

3 Department of ECE, K. G. Reddy College of Engineering & Technology, Hyderabad, Telangana, India.

4 Department of Electronics and Communication Engineering, NIT Kurukshetra, Haryana, India.

Abstract

This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well as gain. It is also found that delay performance of the inverter circuit also gets degraded slightly by using high-k gate dielectric materials. Further, it is observed that the scaling down of channel thickness (TSi) improves the noise margin (NM), and gain (A) at the cost of propagation delay (Pd). Moreover, it is also observed that the changes in noise margin (ΔNM = NM(K=40) – NM(K=3.9)), propagation delay (ΔPd = Pd (K=40) – Pd (K=3.9)), and gain (ΔA = A(K=40) – A(K=3.9)) gets hinder at lower TSi. Therefore, it is apposite to look at lower channel thickness (~6 nm) while designing high-k gate dielectric-based DG-MOSFET for CMOS inverter cell.

Keywords


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