Channel thickness dependency of high-k gate dielectric based double-gate CMOS inverter

Document Type: Reasearch Paper


1 Department of Electronics & Communication Engineering, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.

2 Department of ECE, Ashoka Institute of Engineering & Technology, Hyderabad, Telangana, India.

3 Department of ECE, K. G. Reddy College of Engineering & Technology, Hyderabad, Telangana, India.

4 Department of Electronics and Communication Engineering, NIT Kurukshetra, Haryana, India.


This work investigates the channel thickness dependency of high-k gate dielectric-based complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a conventional double-gate metal gate oxide semiconductor field-effect transistor (DG-MOSFET). It is espied that the use of high-k dielectric as a gate oxide in n/p DG-MOSFET based CMOS inverter results in a high noise margin as well as gain. It is also found that delay performance of the inverter circuit also gets degraded slightly by using high-k gate dielectric materials. Further, it is observed that the scaling down of channel thickness (TSi) improves the noise margin (NM), and gain (A) at the cost of propagation delay (Pd). Moreover, it is also observed that the changes in noise margin (ΔNM = NM(K=40) – NM(K=3.9)), propagation delay (ΔPd = Pd (K=40) – Pd (K=3.9)), and gain (ΔA = A(K=40) – A(K=3.9)) gets hinder at lower TSi. Therefore, it is apposite to look at lower channel thickness (~6 nm) while designing high-k gate dielectric-based DG-MOSFET for CMOS inverter cell.


 [1]    Tayal S., Nandi A., (2018), Performance analysis of junctionless DG-MOSFET based 6T SRAM with gate-stack configuration. Micro Nano Lett. 13: 838-841. 

 [2]    Kuhn K. J., (2012), Consideration for ultimate CMOS scaling. IEEE Trans. Electron Dev. 59: 1813-1828.

 [3]    Zhang W., Fossum J. G., Mathew L., Du Y., (2005), Physical insights regarding design and performance of independent-gate FinFETs. IEEE Trans. Electron Dev. 52: 2198-2206.

 [4]     Tayal S., Nandi A., (2017), Analog/RF performance analysis of inner gate engineered junctionless Si nanotube. Superlatt. Microst. 111: 862-871.

 [5]    Interntional Technology Roadmap for Semiconductor (ITRS) for Radio Frequency and Analog/Mixed-signal Technologies. (2013), [Online]. Available:

 [6]    Mohapatra N. R., Desai M. P., Narendra S. G., Rao V. R., (2002), The effect of high-K gate dielectrics on deep sub-micrometer CMOS device and circuit performance. IEEE Trans. Electron Dev. 49: 826-831.

 [7]    Tayal S., Nandi A., (2017), Analog/RF performance analysis of channel engineered high-k gate-stack based junctionless trigate-FinFET. Superlatt. Microst. 112: 287-295.

 [8]    Momose H. S., Ono M., Yoshitomi T., Ohguro T., Nakamura S.  I., Saito M., Iwai H., (1996), 1.5 nm direct-tunneling gate oxide Si MOSFET’s. IEEE Trans. Electron Dev. 43: 1233-1242.

 [9]    Tayal S., Nandi A., (2017), Study of 6T SRAM cell using high-k gate dielectric based junctionless silicon nanotube FET. Superlatt. Microst. 112: 143-150.

[10]   Ribes G., Mitard J., Denais M., Bruyere S., Monsieur F., Parthasarathy C., Vincent E., Ghibaudo G., (2005), Review on high-K dielectrics reliability issues. IEEE Trans. Dev. Mater. Reliab. 5: 5-19.

[11]   Pradhan K. P., Mohapatra S. K., Sahu P. K., Behera D. K., (2014), Impact of high-K dielectric on analog and RF performance of nanoscale DGMOSFET, Microelectron. J.  45: 144-151.

[12]   Sentarus Device User Guide. [online]. Available:

[13]   Tayal S., Nandi A., (2018), Effect of high-K gate dielectric in-conjunction with channel parameters on the performance of FinFET based 6T SRAM. J. Nanoelectron. Optoelectron. 13: 768-774.

[14]   Tayal S., Nandi A., (2018), Interfacial layer dependence of high-k gate stack based conventional trigate FinFET concerning analog/RF performance, in Proc. of 4th International Conf. on Devices, Circuits and Systems (ICDCS), 305-308.

[15]   Tayal S., Nandi A., (2017), Comparative analysis of high-k gate stack based conventional & junctionless FinFET, in Proc. of 14th IEEE India Council International Conf. (INDICON), 1-4.

[16]   Tayal S., Nandi A., (2017), Effect of FIBL in-conjunction with channel parameters on analog and RF FOM of FinFET. Superlatt. Microst. 105: 152-162.

[17]   Granzner R., Polyakov V. M., Schwierz F., Kittler M., Doll T., (2003), On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs. Phys. E. 19: 33-38.

[18]   Nandi A., Saxena A. K., Dasgupta S., (2016), Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET. Microelectron. J. 55: 19-25.

[19]   Tayal S., Nandi A., (2018), Optimization of gate stack in junctionless Si-nanotube FET for analog/RF applications. Mater Sci Semicond. Process. 80: 63-67.

[20]   Gupta S., Nandi A., (2019), Effect of air spacer in underlap GAA nanowire: An analog/RF prospective, IET Circ Devices Syst. 13: 1196-1202.

[21]   Rabey J. M., Chandrakasan A. P., Nikolic B., (2003), Digital integrated circuits: A Design Perspective, Pearson Education.

[22]   Sachid A. B., Manoj C. R., Sharma D. K., (2008), Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization. IEEE Electron Dev. Lett. 29: 128-130.

[23]   Saini G., Choudhary S., (2016), Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs. Microelectron. J. 58: 1-8.