A fast wallace-based parallel multiplier in quantum-dot cellular automata

Document Type: Reasearch Paper


Department of Computer Engineering, Dezful Branch, Islamic Azad University, Dezful, Iran.


Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technology. Therefore, it is possible to generalize QCA to all digital components. Multipliers are considered as one of the most important building blocks of computational circuits in digital processing systems. The traditional design of multipliers results in wasting the resources and increasing computational time. This paper presents an effective implementation of QCA parallel multiplier based on Wallace tree. It is able to significantly reduce the occupied area by reducing the number of QCA cells and therefore increases the speed of multiplying operation. The proposed QCA multiplier is simulated by QCADesigner2.0.3 software. The simulation results confirm that the proposed QCA multiplier works well and can be used in high performance circuits in QCA technology. Moreover, the proposed QCA multiplier has less complexity and occupied area compared to other QCA multiplier designs.


Main Subjects

[1] Bourianoff G., (2003), The future of nanocomputing. Computer. 36: 44-53.

[2] Haron N. Z., Hamdioui S., Cotofana S., (2009), Emerging non-CMOS nanoelectronic devices-What are they?. 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems. 63-68

[3] Vetteth A., Walus K., Dimitrov V. S., Jullien G. A., (2002), Quantum-dot cellular automata carry-look-ahead adder and barrel shifter. IEEE Emerging Telecommunications Technologies Conference. 2-4.

[4] Lakshmidevi K., Jordhana P. D., (2015), A novel full comparator design using quantum-dot cellular automata. Int. J. VLSI system Design and Communic. Sys. 3: 603-608

[5] Walus K., Jullien G., Dimitrov V., (2003), Computer arithmetic structures for quantum cellular automata. Conf. Record of the Thirty-Seventh Asilomar Conf. on Signals. Sys. Comput. 1435-1439.

[6] Kim S.-W., Swartzlander E. E., (2009), Parallel multipliers for quantum-dot cellular automata. IEEE Nanotechnol. Mater. and Devices Conf. 67-72

[7]­­ Cho H., Swartzlander Jr E. E., (2009), Adder and multiplier design in quantum-dot cellular automata. IEEE Transact. Comput. 58: 721-727.

[8] Vijayalakshmi P.,  Kirthika N., (2012), Design of hybrid adder using QCA with implementation of wallace tree multiplier. Int. J. Adv. Eng. Technol. 3: 202-215.

[9] Lu L., Liu W., O'Neill M., Swartzlander E. E., (2013), QCA systolic array design. IEEE Transact. Comput. 62: 548-560.

[10] Basu S., Bal A., (2014), Realization of combinational multiplier using quantum cellular automata. Int. J. Comput. Applic. 99: 1-6.

[11] Bandani-sousan H. A., Mosleh M., Setayeshi S., (2015), Designing and implementing a fast and robust full-adder in quantum-dot cellular automata (QCA) technology. J. Adv. Comput. Res. 6: 27-45.

[12] Lent C. S., Tougaw P. D., Porod W., Bernstein G. H., (1993), Quantum cellular automata. Nanotechnol. 4: 49-57.

[13] Lent C. S., Tougaw P. D., (1997), A device architecture for computing with quantum dots. Proceed. IEEE. 85: 541-557.

[14] Angizi S., Alkaldy E., Bagherzadeh N., Navi K., (2014), Novel robust single layer wire crossing approach for exclusive or sum of products logic design with quantum-dot cellular automata. J. Low Power Electronics. 10: 259-271.

[15] Bubna M., Mazumdar S., Roy S., Mall R., (2007), Designing cellular automata structures using quantum dot cellular automata. 14th Annual IEEE Int. Conf. High Perf. Computing.

[16] Javid M., Mohamadi K., (2009), Characterization and tolerance of QCA full adder under missing cells defects. Fifth Int. Conf. MEMS, NANO, and Smart Systems. 85-88.

[17] Lakshmi S. K., (2010), Efficient design of logical structures and functions using nanotechnology based quantum dot cellular automata design. Int. J. Comput. Applic. 3: 35-42.

[18]  Lent C. S., Liu M., Lu Y., (2006), Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling. Nanotechnol. 17: 4240-4251.

[19] Wallace C. S., (1964), A suggestion for a fast multiplier. IEEE Transact. Electronic Comput. 1: 14-17.

[20] K'andrea C. B., Schulte M. J., Swartzlander E. E., (1995), Parallel reduced area multipliers. J. VLSI Signal Process. Systems for Signal, Image and Video Technol. 9: 181-191.